1. Field of the Invention
The present invention relates to a method for manufacturing a ceramic laminated substrate by laminating and baking ceramic green sheets.
2. Related Arts
A conventional method for manufacturing a ceramic laminated substrate will be explained referring to FIGS. 1A to 1C. Firstly, via-holes are formed in a ceramic green sheet 101 that is to be a first layer of the laminated substrate, and a conductive material is inserted into the via-holes to form via portions 102 as shown in FIG. 1A. Then, a wiring pattern 103 is formed on the via portions 102. The thus formed green sheet 101 is pressed, thereby being completed. Likewise, via holes are formed in a ceramic green sheet 111 that is to be a second layer, and the via holes are filled with the conductive material, thereby forming via portions 112. Then, after forming a wiring pattern 113 on the via portions 112 as shown in FIG. 1B, the green sheet 112 is completed by pressing. The other green sheets underlying the green sheets 101 and 111 are formed as well.
Next, as shown in FIG. 1C, the green sheets from the first layer to the lowermost layer are laminated by thermo-compression bonding, and then are baked. As a result, the ceramic laminated substrate is obtained. The wiring pattern 103 formed on the surface of the first layer of the ceramic substrate includes a plurality of conductive members for serving as conductive lands electrically connected to electrode terminals of a semiconductor chip or the like mounted on the laminated substrate.
In the above-described method, however, it is difficult to form the wiring pattern accurately on the via portions, resulting in wiring shift as shown in FIG. 1B. Further, when laminating the green sheets 101, 111, . . . , lamination slippage occurs as shown in FIG. 10C. Even if a printing machine having an image recognitive function is employed to form the wiring pattern, it is difficult to prevent the wiring shift of 25 .mu.m at most. (The dimension represents a value after baking the substrate, and hereunder it is the same) Further, even if guide pins are employed to position the green sheets for laminating them, it is difficult to prevent the lamination slippage of 100 .mu.m at most.
Therefore, conventionally, a pitch of the conductive members of the wiring pattern on the via portions and a pitch of the via portions are determined in consideration of the wiring shift and the lamination slippage. For example, in a case that a diameter of each of the via portions is 100 .mu.m, in view of the above-mentioned wiring shift, the wiring pattern on the via portions and the wiring patterns of the underlying green sheets respectively need to have a width of 150 .mu.m at least. Further, the adjacent via portions 102 of the first green sheet 101 are connected to the wiring pattern 113 of the second green sheet 111. Therefore, in view of insulating property, to set the pitch of the wiring pattern 113 on the second green sheet 111 to 50 .mu.m at least, it is necessary to set the pitch of the via portions 102 of the first green sheet 101 to 300 .mu.m at least in the case where each width of the wiring pattern 113 is 150 .mu.m and each diameter of the via portions is 100 .mu.m.
However, a pitch of electrodes of the semiconductor chip mounted on the ceramic laminated substrate has been decreased year by year. Because of this, it is required to reduce the pitch of the via portions of the first green sheets. Especially, in a case that a flip chip IC is connected to the via portions of the first green sheet, the via portions need to be formed at positions substantially corresponding to electrodes of the flip chip IC. A required pitch of the via portions is, for example, 250 .mu.m, and will be 140 .mu.m in the near future. If the above-mentioned method were employed to form a ceramic laminated substrate having via portions with the above-mentioned required pitch, there would arise a problem such that the adjacent via portions short-circuit due to the wiring shift and the lamination slippage as shown in FIG. 1C.